module sign_ext(
  input  [31:0] in,
  input         sign,
  input  [ 1:0] size,
  output [31:0] out
);

assign out =
  {32{size == 2'b00}} & {{24{sign&in[ 7]}},in[ 7:0]} |
  {32{size == 2'b01}} & {{16{sign&in[15]}},in[15:0]} |
  {32{size == 2'b10}} & in;

endmodule
